1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and, more particularly, to a trench isolation method for a semiconductor device.
2. Description of the Related Art
A process of forming an isolation area is initially performed in manufacturing a semiconductor device and is important in determining the size of an active area and a process margin. As the level of integration of a semiconductor device increases, the isolation area becomes smaller, such that a 64M DRAM requires 0.45 micron technology and a 256M DRAM requires 0.25 micron technology. Accordingly, a trench isolation method in which the isolation can be realized in a small area has been widely used.
FIGS. 1 and 2 are sectional views for illustrating a conventional trench isolation.
As shown in FIG. 1, a pad oxide layer 13 and a mask layer 14 defining an active area are sequentially formed on a semiconductor substrate 10. Here, the mask layer 14 is typically formed of a nitride. Then the pad oxide layer 13 and the semiconductor substrate 10 are etched by anisotropic dry-etching using the mask layer 14 as an etching mask, to thereby form a trench 12. Next, to recover damages which were generated during the anisotropic dry-etching a thermal process is performed. Here, a thermal oxide layer 15 is formed on the inner walls of the trench by the thermal process. Preferably, the thickness of the thermal oxide layer 15 is controlled in relation to the depth of the formed trench 12.
In sequence, the pad nitride layer 16 is formed in the trench 12, and then the insulating material 18 is filled therein. The pad nitride layer 16 is formed to relieve a stress which will be generated, during a later thermal process, by the insulating material 18 having a thermal expansion coefficient different from that of the semiconductor substrate.
Referring to FIG. 2, chemical mechanical polishing (CMP) is performed on the entire surface of the semiconductor substrate 10 on which the insulating material 18 is formed until the top surface of the mask layer 14 is exposed using the mask layer 14 as a polishing stopper. When the mask layer 14 exposed through polishing is removed, the trench isolation process by which the active area and the inactive area are divided is completed.
As described above, the conventional trench isolation methods in which two types of material layers lining the inside of the trench 12, ire., the thermal oxide layer 15 and the pad nitride layer 16, are formed before the trench 12 is filled with the insulating material 18 has problems as follows. That is, while the mask layer 14 formed of a nitride layer is removed by phosphorus, the pad nitride layer 16 is partially etched to thereby form an undesirable recess 19 in the trench 12. The recess 19 causes generation of gate poly residue later when a gate is formed, which deteriorates the isolation.
Also, gate poly formed by the later process is filled in a trench edge portion in which the recess 19 is formed. Thus, an active region of the semiconductor substrate 10 is surrounded with the gate poly, so that an electric field is concentrated on the edge of the trench. Accordingly, a threshold voltage of a transistor is dropped. Each of the semiconductor devices requires an optimum threshold voltage. Thus, the drop in the threshold voltage deteriorates the reliability of the semiconductor device. When the threshold voltage value drops below the optimum value, the transistor may malfunction at a low voltage of the optimum operational voltage or less, or charge stored in the capacitor may be lost. The loss of charge means damage to data in a memory cell. This requires that the refresh cycles, in which the lost charge is compensated to keep the data accurate, be shortened.
Two types of U.S. patents have been proposed to solve the above problems as follows.
U.S. Pat. No. 5,436,488 discloses that the reproducibility of an integrated circuit can be increased by increasing the thickness of a gate dielectric layer surrounding a trench corner. In detail, after a trench isolation area has been formed, a thin silicon dioxide (SiO2) film is deposited on the trench isolation area and on an active area adjacent thereto by chemical vapor deposition (CVD). Then, the gate electrode of a transistor is formed on the thin SiO2 film. The thin SiO2 film is interposed between the gate electrode and the trench corner of the transistor. This increases the thickness of the gate dielectric layer, so that the breakdown voltage of the gate dielectric layer is increased at the trench corner.
U.S. Pat. No. 5,447,884 discloses a method for shallow trench isolation which used a nitride liner of 5 nm thickness or less. The nitride liner of 5 nm thickness or less prevents recessing of the nitride liner caused by undesirable voids in the filling material of the trench. During a densification of a thermal oxide layer, in which annealing is performed at 800° C., impurities are removed. Densification as high as that obtained from argon annealing at 1,000° C. can be obtained and thermal load can nearly completely be excluded.
However, in the first U.S. patent, SiO2 is used as a trench liner, and a capping layer filled into a recess generated in a trench corner is formed of SiO2. In the second patent, even though the problems described in the conventional trench isolation method are solved by forming a nitride layer, other problems are presented. First, when the nitride liner is thicker than a predetermined thickness it cannot be used as a gate dielectric layer in an active area. Second, when the nitride layer liner is too thin the nitride layer is undesirably consumed during a pre-plasma process which is performed to enhance the uniformity of USG growth. This undesirable consumption causes oxidation in an oxide layer, under the nitride layer for removing the stress, which deteriorates the performance characteristics of the semiconductor device.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.